
module de0_accel(

	//////////// AVALON SIGNALS //////////
    //50 MHz
	input wire mgmt_clk,
	input wire mgmt_reset_n,
	
	input wire [1:0]mgmt_address,
	input wire [3:0]mgmt_byteen,
	input wire mgmt_write,
	input wire mgmt_read,
	output wire [31:0] mgmt_readdata,
	input wire [31:0] mgmt_writedata,

	
	//////////// Accelerometer exports //////////
	output wire G_SENSOR_CS_N,
	input wire G_SENSOR_INT,
	output wire I2C_SCLK,
	inout I2C_SDAT 
);

//=======================================================
//  PARAMETER declarations
//=======================================================

//=======================================================
//  REG/WIRE declarations
//=======================================================
wire	        dly_rst;
wire	        spi_clk, spi_clk_out;
wire	[15:0]  data_x;


//=======================================================
//  Structural coding
//=======================================================
//	Reset
reset_delay	u_reset_delay	(	
            .iRSTN(mgmt_reset_n),
            .iCLK(mgmt_clk),
            .oRST(dly_rst));

//  PLL            
spipll u_spipll	(
            .areset(dly_rst),
            .inclk0(mgmt_clk),
            .c0(spi_clk),      // 2MHz
            .c1(spi_clk_out)); // 2MHz phase shift 

//  Initial Setting and Data Read Back
spi_ee_config u_spi_ee_config (			
						.iRSTN(!dly_rst),															
						.iSPI_CLK(spi_clk),								
						.iSPI_CLK_OUT(spi_clk_out),								
						.iG_INT2(G_SENSOR_INT),            
						.oDATA_L(data_x[7:0]),
						.oDATA_H(data_x[15:8]),
						.SPI_SDIO(I2C_SDAT),
						.oSPI_CSN(G_SENSOR_CS_N),
						.oSPI_CLK(I2C_SCLK));
						
//	LED
led_driver u_led_driver	(	
						.iRSTN(!dly_rst),
						.iCLK(mgmt_clk),
						.iDIG(data_x[9:0]),
						.iG_INT2(G_SENSOR_INT),            
						.oLED(LED));	

wire [7:0] LED;


// Avalon State 
parameter	IDLE		      =	1'b0;
parameter	DONE		  =	1'b1;

parameter	READ_X		  =	2'b00;



reg avalon_state_c;
reg avalon_state_n;


reg [31:0] readdata_q;
reg [31:0] readdata_d;

always@(posedge mgmt_clk or negedge mgmt_reset_n)
begin
    if(!mgmt_reset_n)
	begin
        avalon_state_c <= IDLE;
        readdata_q <= 32'b1110111;

    end
    else 
    begin
        avalon_state_c <= avalon_state_n;
        
		  if (avalon_state_c == DONE)
		      readdata_q <= readdata_d;
    end
end
	
always @(*)
begin
	 avalon_state_n = IDLE;
	 readdata_d = 32'b11011;

 
    case (avalon_state_c)
        IDLE: 
        begin
            if (mgmt_read)
            begin
                avalon_state_n = DONE;
               
            end
        end
        DONE: 
        begin
				if (mgmt_address == READ_X)
                begin
                    readdata_d = {16'b0, LED};
                end
            avalon_state_n = IDLE;
        end
    endcase
end


assign mgmt_readdata = readdata_q;

endmodule
